1. Field of the Invention
The present invention relates to an image processing apparatus and method and, more specifically, to an image processing apparatus and method for converting image data between a raster scan order and a block scan order.
2. Description of the Related Art
JPEG (Joint Photographic Experts Group) is a compression standard for transmitting still image data such as photographs. JPEG is designed for compressing full-color or gray-scale images, and works well for photographs or art. While another format, GIF (Graphics Interchange Format) allows transmission of color images of 256 colors, JPEG is capable of processing color images in approximately 16 million colors and is more suited to high-resolution display devices. Another advantage of JPEG is that users can control the quality of an image and the size of an image file. For example, when a large-sized image file is compressed into a considerably smaller-sized file, the quality of images may be degraded. However, JPEG compression techniques are capable of compressing images reliably so that compressed images are not lower in quality.
Therefore, JPEG has been widely used for the compression of still image data in such devices as digital still cameras. As is popularly known, JPEG employs a discrete cosine transform (DCT) for compression of data. DCT processes data in a block format of, for example, 8*8 pixels. However, an image data processor of a digital still camera which precedes the DCT processing outputs image data in a raster format (i.e., in a raster scan order, which is from left to right and from top to bottom throughout the image data). FIG. 1A illustrates image data in a raster scan order as output by an image data processor of a digital still camera.
To use JPEG image data stored in a line buffer in a raster format (which is output from the image data processor of the camera as illustrated in FIG. 1A), this data should be read in a block format as shown in FIG. 1B before being supplied to a JPEG compressor. FIG. 1B illustrates image data in a block order format to be input to the JPEG compressor. The conversion from raster scan order to block scan order requires line memories that are capable of storing image data of at least 8 lines. Also, because the image data includes luminance component Y and chrominance components U and V, each color component requires a separate line memory.
FIG. 2 illustrates a conventional line memory system operating under the conventional VGA (Variable Graphics Array) standard for producing an 8*8 block for JPEG compression. An image data processor 10 generates the luminance component Y and chrominance components U and V of the image data in raster format (for example, a 4:2:2 raster format). The image data components Y, U, and V, which are generated from the image data processor 10, are stored in cell arrays of corresponding line memories 12, 14, and 16 by a memory controller. The image data components Y, U, and V, which are stored in the respective line memories 12, 14, and 16 by the image data processor 10, are read in sequences of 8*8 block units to be transferred to a JPEG compressor 20 through a multiplexer 18.
Each line memory 12, 14, and 16 may include additional peripheral circuits for driving the cell arrays of the corresponding line memories 12, 14, and 16. One such example is an address decoder. Thus, there is a great deal of hardware duplication when using multiple line memories. This causes an increase in design costs. Additionally, line memories have become larger and when the line memories are embedded in chips in order to operate a line memory system with low power, the chips also must increase in size. Finally, as the amount of image data increases in size, so must the line memories. As a result, the foregoing problems will grow more serious.
As discussed above, JPEG employs DCT for compression of data and DCT processes data on a block unit of 8*8 pixels and an image data processor of a camera generates image data (in a raster scan order, i.e., from left to right and from top to bottom throughout an image data). Accordingly, conversion of image data of a raster scan order into a block scan order requires a line memory that is capable of storing image data of at least 8 lines. While an image block of 8*8 pixels is produced from the line memory in which the image data of 8 lines are stored, the image data processor of the camera generates new image data. Therefore, a pair of line memory of 8 lines (one to read and one to write) is required to continuously process image data. In other words, while image data is written into one line memory in raster scan order, image data stored in the other line memory is read out in an 8*8 block. Because image data is divided into a luminance component Y and chrominance components U and V, a pair of line memories is needed for each image data component Y, U, V.
FIG. 3A is a schematic block diagram of another conventional VGA-standard image processing apparatus, and illustrates a pairwise line memory system for the luminance component Y only (a pairwise line memory system would also be necessary for each of the chrominance components U and V). Luminance components Y of 8 lines are output from the image data processor 10 and stored linearly into a first line memory Y1 (121). Second luminance components Y of 8 lines are stored linearly into a second line memory Y2 (122), and at the same time a reading operation is performed on the first line memory Y1 on an 8*8 block unit. To accomplish this, switch 181 of MUX 18 is closed and the 8*8 image data block read out from the second line memory Y1 (121) is transferred to the JPEG compressor 20.
FIG. 3B illustrates the pixel order from the image data processor 10 and FIG. 3C illustrates color components Y, U, V stored in their respective line memories 12, 14, and 16.
Write and read addresses of the first and second line memories 121 and 122 are generated by an address generator 24. For a 640×480 VGA image, as illustrated in FIG. 3D, the write address wr_addrline for the line memories 121 and 122 increases from 0 to 640*8-1. The read address rd_addrline for the line memories 121 and 122 for reading out image data in a block unit is set according to Equation 1 below.
for(i=0;i<640/8;i++){for( vv=0;vv<8; vv++){for( hh=0; hh<8; hh++){addr= vv*640+(i*8+ hh)=(vv*80+i)*8+ hh}}}where “640” represents the number of horizontal pixels in the VGA standard, “i” represents the block order, “vv” is a variable represents a vertical pixel (line) of one block, “hh” is a variable representing a horizontal pixel of one block, and (vv*80+i) is an anchor address which holds its value for 8 cycles.
When third luminance components Y of 8 lines are stored into the first line memory Y1 (121) referring to the write address wr_addrline, the switch 181 of MUX 18 is opened and the switch 182 of MUX 18 is closed. A reading operation is performed on the second line memory_Y2 (122) on a block unit referring to the read address, and the read block is transferred to the JPEG compressor 20.
As illustrated and described, the foregoing conventional image processing method uses at least one line memory for each color component and possibly a pair of line memories for each color component. For example, in case of VGA standard, a pair of line memories of 640*8 bytes are used for the luminance component Y, and a pair of line memories of 320*8 bytes for each of the chrominance components U, V. Accordingly, in the event that the line memories are embedded in a chip in order to operate a system with low power, the chip may be increased in size. Still further, as the size of image data increases, the foregoing problem can become more serious.